TO
Product introduction
The abbreviation for Transistor Outline Package, Transistor shape package, is a kind of straight plug package.
Product features
Typically, the transistor shape TO is a plug – in package design. In recent years, surface mount market demand increases, TO packaging also has some progress TO surface mount packaging design.
Application
SOT is one of the most mature industry standard packages used in magnetic induction chips, small appliances, motor drives and other products.
Process characteristics
Refer to or meet JEDEC standards
Customized design lead frame design and multi-specification pad size to meet different customer needs
Green manufacturing, lead-free process
Reliability test standard
The test criteria is zero defects in 77 sampling units
JEDEC Prerequisite: J-STD-20/JESD22-A113
Temperature/humidity test: 85°C/85% RH, JEDEC 22-A101
Temperature/humidity test: 85°C/85% RH, JEDEC 22-A101
Temperature cycle test: -65~150 ℃, JEDEC22-A104
High temperature storage test: 150°C, JEDEC 22-A103
High acceleration stress test: 130°C/85% rh /33.5 PSIA, JEDEC 22-A110/A118
| 序号 | 外型 | 脚数 | 塑封体长 (D)mm | 塑封体宽 (E)mm | 塑封体厚 (A2)mm | 产品总宽 (E1)mm | 脚间距 (e)mm | 脚宽 ( b)mm | 脚长 ( L)mm | 站高 (A1)mm | 最大基岛 尺寸mil | 最大基岛 尺寸um | 框架厚度 mm | 框架 排列 | 默认 包装方式 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | TO92-3L | 3L | 4.10±0.1 | 4.70±0.1 | 1.57±0.1 | 1.27 | 0.40-0.57 | 13.00±0.5 | 129×92 | 3280×2340 | 0.38 | 1×50 | 静电带 | ||
| 2 | TO92S | 3L | 4.0±0.1 | 3.2±0.1 | 1.55±0.1 | 1.27 | 0.35-0.56 | 14.5±0.5 | 62×82 | 1574×2091 | 0.38 | 1×50 | 静电带 | ||
| 3 | TO94L | 4L | 5.22±0.1 | 3.65±0.1 | 1.56±0.1 | 1.27 | 0.40-0.57 | 14.5±0.5 | 152×81 | 3861×2065 | 0.38 | 1×40 | 静电带 |
