{"id":2037,"date":"2022-04-25T11:22:16","date_gmt":"2022-04-25T03:22:16","guid":{"rendered":"http:\/\/hisemi.pcnet.com.cn\/product\/to"},"modified":"2022-05-02T06:42:16","modified_gmt":"2022-05-01T22:42:16","slug":"to-2","status":"publish","type":"product","link":"https:\/\/www.hisemi.com.cn\/en\/product\/to-2","title":{"rendered":"TO"},"content":{"rendered":"\n\n\n\n\t\n\n\t\n\t\n\t
\u5e8f\u53f7<\/th>\u5916\u578b<\/th>\u811a\u6570<\/th>\u5851\u5c01\u4f53\u957f
\n(D)mm<\/th>		\u5851\u5c01\u4f53\u5bbd
\n(E)mm<\/th>		\u5851\u5c01\u4f53\u539a
\n(A2)mm<\/th>		\u4ea7\u54c1\u603b\u5bbd
\n(E1)mm<\/th>		\u811a\u95f4\u8ddd
\n(e)mm<\/th>		\u811a\u5bbd
\n( b)mm<\/th>		\u811a\u957f
\n( L)mm<\/th>		\u7ad9\u9ad8
\n(A1)mm<\/th>		\u6700\u5927\u57fa\u5c9b
\n\u5c3a\u5bf8mil<\/th>		\u6700\u5927\u57fa\u5c9b
\n\u5c3a\u5bf8um<\/th>		\u6846\u67b6\u539a\u5ea6
\nmm<\/th>		\u6846\u67b6
\n\u6392\u5217<\/th>		\u9ed8\u8ba4
\n\u5305\u88c5\u65b9\u5f0f<\/th>\n<\/tr>\n<\/thead>\n
1<\/td>TO92-3L<\/td>3L<\/td>4.10\u00b10.1<\/td>4.70\u00b10.1<\/td>1.57\u00b10.1<\/td><\/td>1.27<\/td>0.40-0.57<\/td>13.00\u00b10.5<\/td><\/td>129\u00d792<\/td>3280\u00d72340<\/td>0.38<\/td>1\u00d750<\/td>\u9759\u7535\u5e26<\/td>\n<\/tr>\n
2<\/td>TO92S<\/td>3L<\/td>4.0\u00b10.1<\/td>3.2\u00b10.1<\/td>1.55\u00b10.1<\/td><\/td>1.27<\/td>0.35-0.56<\/td>14.5\u00b10.5<\/td><\/td>62\u00d782<\/td>1574\u00d72091<\/td>0.38<\/td>1\u00d750<\/td>\u9759\u7535\u5e26<\/td>\n<\/tr>\n
3<\/td>TO94L<\/td>4L<\/td>5.22\u00b10.1<\/td>3.65\u00b10.1<\/td>1.56\u00b10.1<\/td><\/td>1.27<\/td>0.40-0.57<\/td>14.5\u00b10.5<\/td><\/td>152\u00d781<\/td>3861\u00d72065<\/td>0.38<\/td>1\u00d740<\/td>\u9759\u7535\u5e26<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n","protected":false},"excerpt":{"rendered":"

Product introduction<\/strong>
\nThe abbreviation for Transistor Outline Package, Transistor shape package, is a kind of straight plug package.<\/p>\n

Product features<\/strong>
\nTypically, the transistor shape TO is a plug – in package design. In recent years, surface mount market demand increases, TO packaging also has some progress TO surface mount packaging design.<\/p>\n

Application<\/strong>
\nSOT is one of the most mature industry standard packages used in magnetic induction chips, small appliances, motor drives and other products.<\/p>\n

Process characteristics<\/strong>
\nRefer to or meet JEDEC standards
\nCustomized design lead frame design and multi-specification pad size to meet different customer needs
\nGreen manufacturing, lead-free process<\/p>\n

Reliability test standard<\/strong>
\nThe test criteria is zero defects in 77 sampling units
\nJEDEC Prerequisite: J-STD-20\/JESD22-A113
\nTemperature\/humidity test: 85\u00b0C\/85% RH, JEDEC 22-A101
\nTemperature\/humidity test: 85\u00b0C\/85% RH, JEDEC 22-A101
\nTemperature cycle test: -65~150 \u2103, JEDEC22-A104
\nHigh temperature storage test: 150\u00b0C, JEDEC 22-A103
\nHigh acceleration stress test: 130\u00b0C\/85% rh \/33.5 PSIA, JEDEC 22-A110\/A118<\/p>\n

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